Synchronous Transfer Architecture (STA)

This paper presents a novel micro-architecture for high-performance and low-power DSPs. The underlying Synchronous Transfer Architecture (STA) fills the gap between SIMD-DSPs and coarse-grain reconfigurable hardware. STA processors are modeled using a common machine description suitable for both compiler and core generator. The core generator is able to generate models in Lisa, System-C, and VHDL. A special emphasis is placed on the good synthesis of the generated VHDL model.

• Type: Conference
• Year: 2004
• Where: SAMOS
• Authors: Gordon Cichon, Pablo Robelly, Hendrik Seidel, Emil Matús, Marcus Bronzel, Gerhard Fettweis
• Keywords: Coarse-grain Reconfigurable Hardware, Core Generator, SAMOS 2004, Synchronous Transfer Architecture