Instruction Based BIST for Board/System Level Test of External Memories and Internconnects

ct This paper describes a general technique to test external memory/caches and memory interconnects using on-chip logic. Such a test methodology is expected to significantly reduce board/system manufacturing test cost as well as to improve diagnosability of memory and memory-interconnect failures. The proposed methodology incorporates a significant amount of programmability (including programmable MARCH algorithms and data backgrounds) to enable proper testing of all different flavors of memories and caches that one encounters in systems today. Another important aspect of the methodology is its reuse of on-chip memory/cache controllers. This allows the adaptation of the methodology to a variety of memory access protocols (including DDR), without having to re-implement the access protocol inside the BIST engine. These considerations make the External BIST methodology presented in the paper, very general and adaptable to a wide range of applications and their corresponding memory sub-...

• Type: Conference
• Year: 2003
• Where: ITC
• Authors: Olivier Caty, Ismet Bayraktaroglu, Amitava Majumdar, Richard Lee, John Bell, Lisa Curhan
• Keywords: External BIST Methodology, Hardware, ITC 2003, Methodology, Test Methodology