Exact Grading of Multiple Path Delay Faults

The problem of fault grading for multiple path delay faults is studied and a method of obtaining the exact coverage is presented. The faults covered are represented and manipulated as sets by zero-suppressed binary decision diagrams (ZBDD), which are shown to be able to store a very large number of path delay faults. For the extreme case of memory problem, a method to estimate the coverage of the test set is also presented. The problem of fault grading is solved with a polynomial number of BDD operations. Experimental results on the ISCAS’85 benchmark include test sets from ATPG tools and specifically designed tests in order to investigate the limitations and properties of the proposed method.

• Type: Conference
• Year: 2002
• Where: DATE
• Authors: Saravanan Padmanaban, Spyros Tragoudas
• Keywords: DATE 2002, Fault Grading, Hardware, Multiple Path Delay, Path Delay Faults