Power-Aware Design Synthesis Techniques for Distributed Real-Time Systems

This paper presents an end-to-end synthesis technique for lowpower distributed real-time system design. This technique synthesizes supply voltages of resources to optimize system-level power consumption while satisfying end-to-end hard real-time latency bounds. A system is modeled as a set of distributed task chains (or pipelines). Each task chain is given its own end-to-end constraints. Task chains may share resources. Our approach searches the space of the trade-off between end-to-end latency and supply voltages of resources to minimize system-level power consumption. A power optimization algorithm is proposed for simple distributed real-time systems that do not have any resource sharing between task chains, and its optimality is shown. For more general systems, a heuristic based on the same techniques is proposed. Categories and Subject Descriptors B.8.2 [Performance and Reliability]: Performance Analysis and Design Aids General Terms Performance, Design Keywords Real-time, synthes...

• Type: Conference
• Year: 2001
• Where: LCTRTS
• Authors: Dong-In Kang, Stephen P. Crago, Jinwoo Suh
• Keywords: LCTRTS 2001, Supply Voltages, System Software, System-level Power Consumption, Task Chains