Towards a new standard for system-level design

—Huge new design challenges for system-on-chip (SoC) are the result of decreasing time-to-market coupled with rapidly increasing gate counts and embedded software representing 50-90 percent of the functionality. The exchange of system-level intellectual property (IP) models for creating executable specifications has become a key strategic element for efficient system-to-silicon design flows. Because C and C++ are the dominant languages used by chip architects, systems engineers and software engineers today, we believe that a C-based approach to hardware modeling is necessary. This will enable co-design, providing a more natural solution to partitioning functionality between hardware and software. In this paper we present the design of SystemC, a C++ class library that provides the necessary features for modeling design hierarchy, concurrency, and reactivity in hardware. We will also describe experiences of using SystemC 1) for the coverification of 8051 processor with a bus-funct...

• Type: Conference
• Year: 2000
• Where: CODES
• Authors: Stan Y. Liao
• Keywords: CODES 2000, Efficient System-to-silicon Design, Key Strategic Element, Software Engineering, System-level Intellectual Property