Alternative Implementations of Two-Level Adaptive Branch Prediction

As the issue rate and depth of pipelining of high performance Superscalar processors increase, the importance of an excellent branch predictor becomes more vital to delivering the potential performance of a wide-issue, deep pipelined microarchitecture. We propose a new dynamic branch predictor (Two-Level Adaptive Branch Prediction) that achieves substantially higher accuracy than any other scheme reported in the literature. The mechanismuses two levels of branch history information to make predictions, the history of the last k branches encountered, and the branch behavior for the last s occurrences of the speci c pattern of these k branches. We have identi ed three variations of the Two-Level Adaptive Branch Prediction, depending on how nely we resolve the history informationgathered. We compute the hardware costs of implementing each of the three variations, and use these costs in evaluating their relative effectiveness. We measure the branch prediction accuracy of the three variati...

• Type: Conference
• Year: 1998
• Where: ISCA
• Authors: Tse-Yu Yeh, Yale N. Patt
• Keywords: Adaptive Branch Prediction, Hardware, ISCA 1998, Prediction Accuracy, Two-level Adaptive Branch