Useful Application of CMOS Ternary Logic to the Realisation of Asynchronous Circuits

This paper shows how the application of a CMOS ternary logic is useful in the realisation of Delay Insensitive (01)asynchronous circuits. It is shown that fully DIasynchronous circuits are obtained with a ternary handshake protocol which employs the third logic level as idle state of the asynchronous interface. The advantages obtained are a dramatic reduction of the communication requirementand a lowerpower consumption as compared to other asynchronous solutions. It is then discussed how general purpose delay-insensitive circuits can be designed with ternary logic elements and finally an asynchronous sequence recognition circuit is described as application oj the approach. representation. In the Past, it was difficult to obtain nontrivial ternary circuits and so the investigation on asynchronous multivalued logic was discouraged [5]. Recently, improved and reliable CMOS multivalued logic has been reported [6] and its use in asynchronous circuits has been proposed [7]. This paper shows...

• Type: Conference
• Year: 1997
• Where: ISMVL
• Authors: Riccardo Mariani, Roberto Roncella, Roberto Saletti, Pierangelo Terreni
• Keywords: Asynchronous, Hardware, ISMVL 1997, Logic, Ternary Logic