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1997
IEEE

On the Realisation of Delay-Insensitive Asynchronous Circuits with CMOS Ternary Logic

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On the Realisation of Delay-Insensitive Asynchronous Circuits with CMOS Ternary Logic
The realisation of Delay-Insensitive (DI) asynchronous circuits with a CMOS ternary logic is described in this paper. The main advantage of temary logic is the easy realisation of a handshake protocol that significantly reduces the communication requirement, one of the major drawback of asynchronous logic. It is shown how general purpose delay-insensitive circuits are designed with standard ternary logic elements and an original completion detection circuit called watchful. Some elemental circuits (shift-register and adder} are designed and simulated and their performance is compared with other asynchronous solutions, showing that a better performance in term of power consumption has been achieved.
Riccardo Mariani, Roberto Roncella, Roberto Salett
Added 05 Aug 2010
Updated 05 Aug 2010
Type Conference
Year 1997
Where ASYNC
Authors Riccardo Mariani, Roberto Roncella, Roberto Saletti, Pierangelo Terreni
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