Design tool solutions for mixed-signal/RF circuit design in CMOS nanometer technologies

The scaling of CMOS technology into the nanometer era enables the fabrication of highly integrated systems, which increasingly contain analog and/or RF parts. However, scaling into the nanometer era also brings problems of leakage power, increasing variability and degradation, reducing supply voltages and worsening signal integrity conditions, all this in combination with tightening time-tomarket constraints. Design methodologies and tools need to be developed to address these problems. This invited paper describes progress in modeling techniques for design and verification of complex integrated systems, in circuit and yield optimization tools for analog/RF circuits, as well as in signal integrity analysis methods such as EMC/EMI analysis.

• Type: Conference
• Year: 2007
• Where: ASPDAC
• Authors: Georges G. E. Gielen
• Keywords: ASPDAC 2007, Hardware, Nanometer Era, Signal Integrity, Signal Integrity Conditions