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TCAD
2002
137views more  TCAD 2002»
9 years 6 months ago
Generalized traveling-wave-based waveform approximation technique for the efficient signal integrity verification of multicouple
As very large scale integration (VLSI) circuit speed rapidly increases, the inductive effects of interconnect lines strongly impact the signal integrity of a circuit. Since these i...
Yungseon Eo, Seongkyun Shin, William R. Eisenstadt...
ASPDAC
2007
ACM
136views Hardware» more  ASPDAC 2007»
9 years 10 months ago
Design tool solutions for mixed-signal/RF circuit design in CMOS nanometer technologies
The scaling of CMOS technology into the nanometer era enables the fabrication of highly integrated systems, which increasingly contain analog and/or RF parts. However, scaling into...
Georges G. E. Gielen
DATE
1998
IEEE
91views Hardware» more  DATE 1998»
9 years 11 months ago
Interconnect Tuning Strategies for High-Performance Ics
Interconnect tuning is an increasingly critical degree of freedom in the physical design of high-performance VLSI systems. By interconnect tuning, we refer to the selection of lin...
Andrew B. Kahng, Sudhakar Muddu, Egino Sarto, Rahu...
VLSID
1999
IEEE
104views VLSI» more  VLSID 1999»
9 years 11 months ago
Interconnect Optimization Strategies for High-Performance VLSI Designs
Interconnect tuning and repeater insertion are necessary to optimize interconnectdelay, signalperformanceandintegrity, andinterconnectmanufacturability and reliability. Repeater i...
Andrew B. Kahng, Sudhakar Muddu, Egino Sarto
ISCAS
1999
IEEE
102views Hardware» more  ISCAS 1999»
9 years 11 months ago
Power and signal integrity improvement in ultra high-speed current mode logic
Current mode (ECL) logic has long been the option of choice in those applications requiring logic functions at multigigahertz rates. This trend continues despite the obvious very ...
Hien Ha, Forrest Brewer
DSD
2002
IEEE
96views Hardware» more  DSD 2002»
9 years 11 months ago
Networks on Silicon: Blessing or Nightmare?
Continuing VLSI technology scaling raises several deep submicron (DSM) problems like relatively slow interconnect, power dissipation and distribution, and signal integrity. Those ...
Paul Wielage, Kees G. W. Goossens
DATE
2003
IEEE
90views Hardware» more  DATE 2003»
10 years 2 days ago
Extending JTAG for Testing Signal Integrity in SoCs
As the technology is shrinking and the working frequency is going into multi gigahertz range, the issues related to interconnect testing are becoming more dominant. Speci´Čücally,...
Nisar Ahmed, Mohammad H. Tehranipour, Mehrdad Nour...
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