An adaptive Reed-Solomon errors-and-erasures decoder

The development of Reed-Solomon (RS) codes has allowed for improved data transmission over a variety of communication media. Although Reed-Solomon decoding provides a powerful defense against burst data errors, the significant circuit area and power consumption of customized RS decoder hardware can be limiting for embedded computing environments. To support enhanced performance decoding with minimal power consumption, a dynamicallyreconfigurable FPGA-based Reed-Solomon decoder has been developed. Our errors-and-erasures decoding system uses multiple erasure blocks to identify the location of likely corrupted data and multiple decoders to attempt error correction. The RS decoder design is implemented in reconfigurable hardware to leverage architectural parallelism and specialization. Run-time dynamic reconfiguration of the decoding system is used in response to variations in channel conditions to support the fastest possible data rate while, as a secondary metric, minimizing decoder po...

• Type: Conference
• Year: 2006
• Where: FPGA
• Authors: Lilian Atieno, Jonathan Allen, Dennis Goeckel, Russell Tessier
• Keywords: Decoder, FPGA, FPGA 2006, Power Consumption, Reed-Solomon