Simulation of the effects of timing jitter in track-and-hold and sample-and-hold circuits

In this paper, we analyze the effect of jitter in track and hold circuits. The output spectrum is obtained in terms of the system function of the track and hold. It is a fairly general model in which the effect of input as well as clock jitter can be included. The clock can have an arbitrary duty cycle, so that the circuit could also approximate a sample and hold. Using this model, it is possible to simulate the effects of jitter in a track and hold using a standard circuit simulator. Three cases are analyzed - long term jitter, correlated jitter with exponential autocorrelation and white noise jitter. These results are verified using Monte Carlo simulations. Categories and Subject Descriptors: B.7.2 Design Aids: Simulation General Terms:Design

• Type: Conference
• Year: 2005
• Where: DAC
• Authors: V. Vasudevan
• Keywords: Clock Jitter, Computer Architecture, DAC 2005, Jitter, Long Term Jitter