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10

ISLPED
2007
ACM

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A low-power SRAM using bit-line charge-recycling technique

13 years 5 months ago

A low-power SRAM using bit-line charge-recycling technique

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We propose a new low-power SRAM using bit-line Charge Recycling (CR-SRAM) for the write operation. In the proposed write scheme, differential voltage swing of a bit-line is obtained by recycled charge from its adjacent bit-line capacitance. In order to improve the data retention capability of un-selected cells during write, the power supply lines of memory cells in one column are connected to each other and separated from the power lines of other columns. A test-chip is fabricated in 0.13μm CMOS and measurement results show 88% reduction in total power

Keejong Kim, Hamid Mahmoodi, Kaushik Roy

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Adjacent Bit-line Capacitance | Hardware | ISLPED 2007 | Power Supply Lines | Write Operation |

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Added	26 Oct 2010
Updated	26 Oct 2010
Type	Conference
Year	2007
Where	ISLPED
Authors	Keejong Kim, Hamid Mahmoodi, Kaushik Roy

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