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ISQED
2008
IEEE

Error-Tolerant SRAM Design for Ultra-Low Power Standby Operation

12 years 6 months ago
Error-Tolerant SRAM Design for Ultra-Low Power Standby Operation
We present an error-tolerant SRAM design optimized for ultra-low standby power. Using SRAM cell optimization techniques, the maximum data retention voltage (DRV) of a 90nm 26kb SRAM module is reduced from 550mV to 220mV. A novel errortolerant architecture further reduces the minimum static-error-free VDD to 155mV. With a 100mV noise margin, a 255mV standby VDD effectively reduces the SRAM leakage power by 98% compared to the typical standby at 1V VDD.
Huifang Qin, Animesh Kumar, Kannan Ramchandran, Ja
Added 31 May 2010
Updated 31 May 2010
Type Conference
Year 2008
Where ISQED
Authors Huifang Qin, Animesh Kumar, Kannan Ramchandran, Jan M. Rabaey, Prakash Ishwar
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