MYGEN: automata-based on-line test generator for assertion-based verification

To assist in dynamic assertion-based verification, we present a method to automatically build a test vector generator from a temporal property. Based on the duality between monitors and generators, we have extended the monitor generator tool MBAC to produce synthesizable on-line generators. We have tested the resulting generators in simulation and by emulation on an FPGA. The combination of multiple generators provides an efficient way to model the environment of modules within a DUT, facilitating an equivalent of software "unit testing" under real conditions, early in the design flow. Categories and Subject Descriptors B.2.3 [Reliability, Testing, and Fault-Tolerance]: Error-checking-Test generation; B.5.2 [Design Aids]: Verification General Terms Verification Keywords Test vector generation, semi-formal verification, PSL, generator

• Type: Journal
• Year: 2009
• Where: GLVLSI
• Authors: Yann Oddos, Katell Morin-Allory, Dominique Borrione, Marc Boule, Zeljko Zilic
• Keywords: Dynamic Assertion-based Verification, Generators, GLVLSI 2009, Test Vector, VLSI