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8

VLSID
2004
IEEE

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High-Performance Power Grids For Nanometer Technologies

14 years 4 months ago

High-Performance Power Grids For Nanometer Technologies

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With shrinking noise margins and increasing numbers of on-chip noise sources, power grid design has become a critical performance determinant. This paper presents an overview of recent techniques for the analysis and optimization of supply networks, and discusses future trends in power grid design.

Sachin S. Sapatnekar

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Computer Architecture | Critical Performance Determinant | On-chip Noise Sources | Power Grid Design | VLSID 2004 |

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Added	01 Dec 2009
Updated	01 Dec 2009
Type	Conference
Year	2004
Where	VLSID
Authors	Sachin S. Sapatnekar

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