7 search results - page 1 / 2 » High-Performance Power Grids For Nanometer Technologies |
VLSID
2004
IEEE
14 years 5 months ago
2004
IEEE
With shrinking noise margins and increasing numbers of on-chip noise sources, power grid design has become a critical performance determinant. This paper presents an overview of r...
JCP
2008
13 years 4 months ago
2008
In this paper a new low power and high performance adder cell using a new design style called "Bridge" is proposed. The bridge design style enjoys a high degree of regula...
DAC
2003
ACM
14 years 5 months ago
2003
ACM
Power dissipation is becoming the most challenging design constraint in nanometer technologies. Among various design implementation schemes, standard cell ASICs offer the best pow...
ICCAD
2007
IEEE
14 years 1 months ago
2007
IEEE
Abstract— This paper addresses the module assignment problem in pinlimited designs under the stacked-Vdd circuit paradigm. A partition-based algorithm is presented for efficient...
HPCA
2009
IEEE
13 years 11 months ago
2009
IEEE
As transistor process technology approaches the nanometer scale, process variation significantly affects the design and optimization of high performance microprocessors. Prior stu...