Sciweavers

Free Online Productivity Tools i2Speak i2Symbol i2OCR iTex2Img iWeb2Print iWeb2Shot i2Type iPdf2Split iPdf2Merge i2Bopomofo i2Arabic i2Style i2Image i2PDF iLatex2Rtf Sci2ools

7

VLSID
2004
IEEE

favoriteEmaildiscussreport

89views VLSI» more VLSID 2004»

Response Surface Modeling of 100nm CMOS Process Technology using Design of Experiment

14 years 4 months ago

Response Surface Modeling of 100nm CMOS Process Technology using Design of Experiment

Download eprints.iisc.ernet.in

H. C. Srinivasaiah, Navakanta Bhat

Real-time Traffic

CMOS Process Technology | Computer Architecture | VLSID 2004 |

claim paper

Related Content

» A New Method for Design of Robust Digital Circuits

» Parameter Reduction for Variability Analysis by Slice Inverse Regression SIR Method

» ProjectionBased PiecewiseLinear Response Surface Modeling for Strongly Nonlinear VLSI Perf...

» Implementation of response surface methodology using variance reduction techniques in semi...

» Towards Process Models for Disaster Response

» Efficient statistical analysis of read timing failures in SRAM circuits

» Use of Simulation in Optimization of Maintenance Policies

» A proposed metric for assessing the measurement quality of individual microarrays

» Quadratic variance models for adaptively preprocessing SELDITOF mass spectrometry data

Post Info
More Details (n/a)

Added	01 Dec 2009
Updated	01 Dec 2009
Type	Conference
Year	2004
Where	VLSID
Authors	H. C. Srinivasaiah, Navakanta Bhat

Comments (0)