Challenges in the Design of a Scalable Data-Acquisition and Processing System-on-Silicon

Increasing complexity of the functionalities and the resultant growth in number of gates integrated in a chip coupled with shrinking geometries and short cycle time requirements bring in several challenges into the design of present day VLSI chips. In this paper we present the challenges faced and the approaches successfully adopted in the design of a complex 2.5 million gate high bandwidth data acquisition and processing VLSI chip (a trace-receiver chip, code-named Drishti) in a deep sub-micron technology at Texas Instruments India. The very high design complexity arises due to the rich architecture of the trace-receiver chip, the aggressive timing and performance requirements and its large size. The trace-receiver chip is highly configurable and scalable, thereby catering to both low-end systems, which are cost sensitive, and high-end applications, which demand performance. We present the innovative approaches that were applied to address the challenges encountered in meeting the agg...

• Type: Conference
• Year: 2002
• Where: VLSID
• Authors: Karanth Shankaranarayana, Soujanna Sarkar, R. Venkatraman, Shyam S. Jagini, N. Venkatesh, Jagdish C. Rao, H. Udayakumar, M. Sambandam, K. P. Sheshadri, S. Talapatra, Parag Mhatre, Jais Abraham, Rubin A. Parekhji
• Keywords: Aggressive Design Goals, Computer Architecture, Design Complexity Arises, Trace-receiver Chip, VLSID 2002