Toward an Integrated Design Methodology for Fault-Tolerant, Multiple Clock/Voltage Integrated Systems

Abstract - This paper describes a communicationcentric design methodology that addresses the fundamental challenges induced by the emergence of truly heterogeneous Systems-on-Chip (SoCs). For such systems, the globally asynchronous design paradigm seems to be the most promising (if not the only) solution for providing an underlying substrate for cost-effective and power efficient on-chip communication among diverse, mixed technology IPs. Additional challenges are related to reliability and error resilience of on-chip communication architectures. The proposed on-chip communication methodology targets all levels of ion, from circuit, to microarchitecture and system-level by seamlessly integrating solutions for robust and efficient globally asynchronous communication among diverse IPs.

• Type: Conference
• Year: 2004
• Where: ICCD
• Authors: Radu Marculescu, Diana Marculescu, Larry T. Pileggi
• Keywords: Efficient On-chip Communication, Hardware, ICCD 2004, On-chip Communication Architectures, On-chip Communication Methodology