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ICCD
2004
IEEE
103views Hardware» more  ICCD 2004»
9 years 10 months ago
A Fast Delay Analysis Algorithm for The Hybrid Structured Clock Network
This paper presents a novel approach to reducing the complexity of the transient linear circuit analysis for a hybrid structured clock network. Topology reduction is first used to...
Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheld...
ICCD
2004
IEEE
115views Hardware» more  ICCD 2004»
9 years 10 months ago
ACG-Adjacent Constraint Graph for General Floorplans
ACG (Adjacent Constraint Graph) is invented as a general floorplan representation. It has advantages of both adjacency graph and constraint graph of a floorplan: edges in an ACG...
Hai Zhou, Jia Wang
ICCD
2004
IEEE
119views Hardware» more  ICCD 2004»
9 years 10 months ago
Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing
We present a method for incorporating crosstalk reduction criteria into global routing under an innovative power supply architecture, while considering the constraints imposed by ...
Tianpei Zhang, Sachin S. Sapatnekar
ICCD
2004
IEEE
129views Hardware» more  ICCD 2004»
9 years 10 months ago
Cache Array Architecture Optimization at Deep Submicron Technologies
A cache access time model, PRACTICS (PRedictor of Access and Cycle TIme for Cache Stack), has been developed to optimize the memory array architecture for the minimum access and c...
Annie (Yujuan) Zeng, Kenneth Rose, Ronald J. Gutma...
ICCD
2004
IEEE
91views Hardware» more  ICCD 2004»
9 years 10 months ago
Diagnosis of Hold Time Defects
In modern technologies, process variations can be quite substantial, often causing design timing failures. It is essential that those errors be correctly and quickly diagnosed. In...
Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han T...
ICCD
2004
IEEE
111views Hardware» more  ICCD 2004»
9 years 10 months ago
Potential Slack Budgeting with Clock Skew Optimization
Potential slack is an effective metric of circuit’s possible performance improvement. It is equal to the maximal amount of slack that can be potentially used for optimization. I...
Kai Wang, Malgorzata Marek-Sadowska
ICCD
2004
IEEE
137views Hardware» more  ICCD 2004»
9 years 10 months ago
Comparative Study of Strategies for Formal Verification of High-Level Processors
Compared are different methods for evaluation of formulas expressing microprocessor correctness in the logic of Equality with Uninterpreted Functions and Memories (EUFM) by transl...
Miroslav N. Velev
ICCD
2004
IEEE
114views Hardware» more  ICCD 2004»
9 years 10 months ago
Low Energy, Highly-Associative Cache Design for Embedded Processors
Many embedded processors use highly associative data caches implemented using a CAM-based tag search. When high-associativity is desirable, CAM designs can offer performance advan...
Alexander V. Veidenbaum, Dan Nicolaescu
ICCD
2004
IEEE
154views Hardware» more  ICCD 2004»
9 years 10 months ago
Transistor and Pin Reordering for Gate Oxide Leakage Reduction in Dual T{ox} Circuits
Gate oxide tunneling current (Igate) is emerging as a key roadblock for device scaling in nanometer-scale CMOS circuits. A practical means to reduce Igate is to leverage dual Tox ...
Anup Kumar Sultania, Dennis Sylvester, Sachin S. S...
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