Performance Efficiency of Context-Flow System-on-Chip Platform

Recent efforts in adapting computer networks into system-on-chip (SOC), or network-on-chip, present a setback to the traditional computer systems for the lack of effective programming model, while not taking full advantage of the almost unlimited on-chip bandwidth. In this paper, we propose a new programming model, called context-flow, that is simple, safe, highly parallelizable yet transparent to the underlying architectural details. An SOC platform architecture is then designed to support this programming model, while fully exploiting the physical proximity between the processing elements. We demonstrate the performance efficiency of this architecture over bus based and packet-switch based networks by two case studies using a multi-processor architecture simulator.

• Type: Conference
• Year: 2003
• Where: ICCAD
• Authors: Rami Beidas, Jianwen Zhu
• Keywords: Hardware, ICCAD 2003, Multi-processor Architecture Simulator, Programming Model, SOC Platform Architecture