Scalable compile-time scheduler for multi-core architectures

As the number of cores continues to grow in both digital signal and general purpose processors, tools which perform automatic scheduling from model-based designs are of increasing interest. This scheduling consists of statically distributing the tasks that constitute an application between available cores in a multi-core architecture in order to minimize the final latency. This problem has been proven to be NP-complete. A static scheduling algorithm is usually described as a monolithic process, and carries out two distinct functionalities: choosing the core to execute a specific function and evaluating the cost of the generated solutions. This paper describes a scheduling module which splits these functionalities into two sub-modules. This division produces an advanced scalability in terms of schedule quality and computation time, and also separates the heuristic complexity from the architecture model precision.

• Type: Conference
• Year: 2009
• Where: DATE
• Authors: Maxime Pelcat, Pierrick Menuet, Slaheddine Aridhi, Jean-François Nezan
• Keywords: Automatic Scheduling, DATE 2009, General Purpose Processors, Hardware, Static Scheduling Algorithm