Sciweavers

ISCA
2009
IEEE

Phastlane: a rapid transit optical routing network

13 years 10 months ago
Phastlane: a rapid transit optical routing network
Tens and eventually hundreds of processing cores are projected to be integrated onto future microprocessors, making the global interconnect a key component to achieving scalable chip performance within a given power envelope. While CMOS-compatible nanophotonics has emerged as a leading candidate for replacing global wires beyond the 22nm timeframe, on-chip optical interconnect architectures proposed thus far are either limited in scalability or are dependent on comparatively slow electrical control networks. In this paper, we present Phastlane, a hybrid electrical/optical routing network for future large scale, cache coherent multicore microprocessors. The heart of the Phastlane network is a lowlatency optical crossbar that uses simple predecoded source routing to transmit cache-line-sized packets several hops in a single clock cycle under contentionless conditions. When contention exists, the router makes use of electrical buffers and, if necessary, a high speed drop signaling networ...
Mark J. Cianchetti, Joseph C. Kerekes, David H. Al
Added 24 May 2010
Updated 24 May 2010
Type Conference
Year 2009
Where ISCA
Authors Mark J. Cianchetti, Joseph C. Kerekes, David H. Albonesi
Comments (0)