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MICRO
2009
IEEE
134views Hardware» more  MICRO 2009»
9 years 8 months ago
A case for dynamic frequency tuning in on-chip networks
Performance and power are the first order design metrics for Network-on-Chips (NoCs) that have become the de-facto standard in providing scalable communication backbones for mult...
Asit K. Mishra, Reetuparna Das, Soumya Eachempati,...
MICRO
2009
IEEE
103views Hardware» more  MICRO 2009»
9 years 8 months ago
BulkCompiler: high-performance sequential consistency through cooperative compiler and hardware support
A platform that supported Sequential Consistency (SC) for all codes — not only the well-synchronized ones — would simplify the task of programmers. Recently, several hardware ...
Wonsun Ahn, Shanxiang Qi, M. Nicolaides, Josep Tor...
MICRO
2009
IEEE
148views Hardware» more  MICRO 2009»
9 years 8 months ago
Flip-N-Write: a simple deterministic technique to improve PRAM write performance, energy and endurance
The phase-change random access memory (PRAM) technology is fast maturing to production levels. Main advantages of PRAM are non-volatility, byte addressability, in-place programmab...
Sangyeun Cho, Hyunjin Lee
MICRO
2009
IEEE
178views Hardware» more  MICRO 2009»
9 years 8 months ago
Improving cache lifetime reliability at ultra-low voltages
Voltage scaling is one of the most effective mechanisms to reduce microprocessor power consumption. However, the increased severity of manufacturing-induced parameter variations a...
Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerso...
MICRO
2009
IEEE
326views Hardware» more  MICRO 2009»
9 years 8 months ago
DDT: design and evaluation of a dynamic program analysis for optimizing data structure usage
Data structures define how values being computed are stored and accessed within programs. By recognizing what data structures are being used in an application, tools can make app...
Changhee Jung, Nathan Clark
MICRO
2009
IEEE
121views Hardware» more  MICRO 2009»
9 years 8 months ago
Application-aware prioritization mechanisms for on-chip networks
Network-on-Chips (NoCs) are likely to become a critical shared resource in future many-core processors. The challenge is to develop policies and mechanisms that enable multiple ap...
Reetuparna Das, Onur Mutlu, Thomas Moscibroda, Chi...
MICRO
2009
IEEE
120views Hardware» more  MICRO 2009»
9 years 8 months ago
Reducing peak power with a table-driven adaptive processor core
The increasing power dissipation of current processors and processor cores constrains design options, increases packaging and cooling costs, increases power delivery costs, and de...
Vasileios Kontorinis, Amirali Shayan, Dean M. Tull...
MICRO
2009
IEEE
129views Hardware» more  MICRO 2009»
9 years 8 months ago
In-network coherence filtering: snoopy coherence without broadcasts
With transistor miniaturization leading to an abundance of on-chip resources and uniprocessor designs providing diminishing returns, the industry has moved beyond single-core micr...
Niket Agarwal, Li-Shiuan Peh, Niraj K. Jha
MICRO
2009
IEEE
168views Hardware» more  MICRO 2009»
9 years 8 months ago
Ordering decoupled metadata accesses in multiprocessors
Hardware support for dynamic analysis can minimize the performance overhead of useful applications such as security checks, debugging, and profiling. To eliminate implementation ...
Hari Kannan
MICRO
2009
IEEE
115views Hardware» more  MICRO 2009»
9 years 8 months ago
SHARP control: controlled shared cache management in chip multiprocessors
Shekhar Srikantaiah, Mahmut T. Kandemir, Qian Wang
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