Current source based standard cell model for accurate signal integrity and timing analysis

— The inductance and coupling effects in interconnects and non-linear receiver loads has resulted in complex input signals and output loads for gates in the modern deep submicron CMOS technologies. As a result, the conventional method of timing characterization, which is based on lookup tables with input slew and output load capacitance as indices, is no longer adequate. The focus has now shifted to current source based standard cell models which are based on the fundamental property of transconductance of MOSFETs. In this paper 1 we propose a systematic methodology for obtaining a current based delay model for gates, which can accommodate both single (SIS) and multi-input (MIS) switching signals of arbitrary shape and complex non-linear output loads. We use an analytical model for the gate output current expressed as a function of the node voltages. This results in an average error less than 0.5% with maximum standard deviation of 2.5% in error when compared with SPICE for a large n...

• Type: Conference
• Year: 2008
• Where: DATE
• Authors: Amit Goel, Sarma B. K. Vrudhula
• Keywords: DATE 2008, Hardware, Non-linear Output Loads, Non-linear Receiver Loads, Output Load