Sciweavers
Explore
Publications
Books
Software
Tutorials
Presentations
Lectures Notes
Datasets
Labs
Conferences
Community
Upcoming
Conferences
Top Ranked Papers
Most Viewed Conferences
Conferences by Acronym
Conferences by Subject
Conferences by Year
Tools
Sci2ools
International Keyboard
Graphical Social Symbols
CSS3 Style Generator
OCR
Web Page to Image
Web Page to PDF
Merge PDF
Split PDF
Latex Equation Editor
Extract Images from PDF
Convert JPEG to PS
Convert Latex to Word
Convert Word to PDF
Image Converter
PDF Converter
Community
Sciweavers
About
Terms of Use
Privacy Policy
Cookies
Free Online Productivity Tools
i2Speak
i2Symbol
i2OCR
iTex2Img
iWeb2Print
iWeb2Shot
i2Type
iPdf2Split
iPdf2Merge
i2Bopomofo
i2Arabic
i2Style
i2Image
i2PDF
iLatex2Rtf
Sci2ools
3
click to vote
DATE
2008
IEEE
favorite
Email
discuss
report
139
views
Hardware
»
more
DATE 2008
»
Analysis of The Test Data Volume Reduction Benefit of Modular SOC Testing
13 years 11 months ago
Download
www.date-conference.com
Ozgur Sinanoglu, Erik Jan Marinissen
Real-time Traffic
DATE 2008
|
Hardware
|
claim paper
Related Content
»
An novel Methodology for Reducing SoC Test Data Volume on FPGAbased Testers
»
Test Resource Partitioning and Reduced PinCount Testing Based on Test Data Compression
»
Scan Power Reduction Through Test Data Transition Frequency Analysis
»
Test Data Compression The System Integrators Perspective
»
High volume microprocessor test escapes an analysis of defects our tests are missing
»
Industrial Experience with Adoption of EDT for LowCost Test without Concessions
»
Test application time and volume compression through seed overlapping
»
A Reconfigurable Shared Scanin Architecture
»
ATPG Padding And ATE Vector Repeat Per Port For Reducing Test Data Volume
more »
Post Info
More Details (n/a)
Added
29 May 2010
Updated
29 May 2010
Type
Conference
Year
2008
Where
DATE
Authors
Ozgur Sinanoglu, Erik Jan Marinissen
Comments
(0)
Researcher Info
Hardware Study Group
Computer Vision