A distributed processor state management architecture for large-window processors

— Processor architectures with large instruction windows have been proposed to expose more instruction-level parallelism (ILP) and increase performance. Some of the proposed architectures replace a re-order buffer (ROB) with a check-pointing mechanism and an out-of-order release of processor resources. Check-pointing, however, leads to an imprecise processor state recovery on mis-predicted branches and exceptions and re-execution of correct-path instructions after state recovery. It also requires large register files complicating renaming, allocation and release of physical registers. This paper proposes a new processor architecture called a MultiState Processor (MSP). The MSP does not use check-pointing, avoids the above-mentioned problems, and has a fast, distributed state recovery mechanism. The MSP uses a novel register management architecture allowing implementation of large register files with simpler and more scalable register allocation, renaming, and release. It is also key ...

• Type: Conference
• Year: 2008
• Where: MICRO
• Authors: Isidro Gonzalez, Marco Galluzzi, Alexander V. Veidenbaum, Marco A. Ramírez, Adrián Cristal, Mateo Valero
• Keywords: Hardware, MICRO 2008, Processor State Recovery, Register File, State Recovery