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DATE
2006
IEEE

4G applications, architectures, design methodology and tools for MPSoC

9 years 12 months ago
4G applications, architectures, design methodology and tools for MPSoC
transistors the design of the SoC needs to be moved to a higher level of abstraction. We need to think in processors and interconnects rather than gates and wires. We discuss the need for a system level design methodology and the corresponding design environment and outline the properties of the new system level design paradigm 3.2 Future Telecommunication Systems We discuss the architecture of 4G and potential applications. We introduce the concepts of software defined and cognitive radio. 3.3 MPSoC for wireless applications We argue that future system-on-chips (SocCs) will be viewed as heterogeneous multiprocessor systems (MPSoC). They will contain an increasing number of application specific instruction-set processors (ASIPs) combined with complex memory hierarchies and on-chip communication networks. These heterogeneous architectures promise enormous 3-9810801-0-6/DATE06 © 2006 EDAA
Added 10 Jun 2010
Updated 10 Jun 2010
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Year 2006
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