65NM sub-threshold 11T-SRAM for ultra low voltage applications

In this paper a new ultra low power SRAM cell is proposed. In the proposed SRAM topology, additional circuitry has been added to a standard 6T-SRAM cell to improve the static noise margin (SNM) and the performance. Foundry models for a 65 nm standard CMOS process were used for obtaining reliable simulated results. The circuit was simulated for supply voltages from 0.2V to 0.35V verifying the robustness of the proposed circuit for different supply voltages. The simulations show a significant improvement in SNM and a 4X improvement in read speed still maintaining a satisfactory write noise margin compared with the 6TSRAM cell. The proposed circuit has an area overhead between 22%-28% compared with the 6T-SRAM.

• Type: Conference
• Year: 2008
• Where: SOCC
• Authors: Farshad Moradi, Dag T. Wisland, Snorre Aunet, Hamid Mahmoodi, Tuan Vu Cao
• Keywords: Education, Noise Margin, Power Sram Cell, SOCC 2008, Supply Voltages