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ISQED
2009
IEEE

New subthreshold concepts in 65nm CMOS technology

10 years 11 months ago
New subthreshold concepts in 65nm CMOS technology
In this paper challenges observed in 65nm technology for circuits utilizing subthreshold region operation are presented. Different circuits are analyzed and simulated for ultra low supply voltages to find the best topology for subthreshold operation. To support the theoretical discussions different topologies are analyzed and simulated. Various aspects of flip-flop circuits are described in detail to study which topology would be most suitable for ultra low supply voltage and low-power applications. Simulation results show that the power consumption decreases by at least 23% compared with other flip-flops. Also, the setup time and the hold time are improved. Keywords Low-voltage, low-power, subthreshold, nanoscale
Farshad Moradi, Dag T. Wisland, Hamid Mahmoodi, Al
Added 19 May 2010
Updated 19 May 2010
Type Conference
Year 2009
Where ISQED
Authors Farshad Moradi, Dag T. Wisland, Hamid Mahmoodi, Ali Peiravi, Snorre Aunet, Tuan Vu Cao
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