Sciweavers

Share
DAC
2006
ACM

An adaptive FPGA architecture with process variation compensation and reduced leakage

10 years 24 days ago
An adaptive FPGA architecture with process variation compensation and reduced leakage
Process induced threshold voltage variations bring about fluctuations in circuit delay, that affect the FPGA timing yield. We propose an adaptive FPGA architecture that compensates for these fluctuations. The architecture includes an additional characterizer circuit that classifies logic and routing blocks on each die according to their performance. Based on this classification, the architecture adaptively body-biases these resources by either speeding up the slow blocks or by slowing down the leaky ones. This procedure mitigates the effect of the variations and provides a better yield. We further diminish leakage by slowing down areas of the FPGA that have a positive slack. Overall, this architecture minimizes the timing variance of within-die and die-to-die Vth variations by up to 3.45X and reduces leakage power in the non-critical areas of the FPGA by 3X with no effect on frequency. Categories and Subject Descriptors B.3.1 [Integrated Circuits]: Types and Design Styles General Term...
Georges Nabaa, Navid Azizi, Farid N. Najm
Added 13 Nov 2009
Updated 13 Nov 2009
Type Conference
Year 2006
Where DAC
Authors Georges Nabaa, Navid Azizi, Farid N. Najm
Comments (0)
books