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VLSID
1999
IEEE
91views VLSI» more  VLSID 1999»
9 years 9 months ago
Timed Circuit Synthesis Using Implicit Methods
The design and synthesis of asynchronous circuits is gaining importance in both the industrial and academic worlds. Timed circuits are a class of asynchronous circuits that incorp...
Robert Thacker, Wendy Belluomini, Chris J. Myers
VLSID
1999
IEEE
101views VLSI» more  VLSID 1999»
9 years 9 months ago
Formal System Design Based on the Synchrony Hypothesis, Functional Models and Skeletons
Formal approaches to HW and system design have not been generally adopted, because designers often view the modelling concepts in these approaches as unsuitable for their problems...
Ingo Sander, Axel Jantsch
VLSID
1999
IEEE
139views VLSI» more  VLSID 1999»
9 years 9 months ago
Processor Modeling for Hardware Software Codesign
In hardware - software codesign paradigm often a performance estimation of the system is needed for hardware - software partitioning. The tremendous growth of application specific...
V. Rajesh, Rajat Moona
VLSID
1999
IEEE
122views VLSI» more  VLSID 1999»
9 years 9 months ago
Formal Verification of an ARM Processor
This paper presents a detailed description of the application of a formal verification methodology to an ARM processor. The processor, a hybrid between the ARM7 and the StrongARM ...
Vishnu A. Patankar, Alok Jain, Randal E. Bryant
VLSID
1999
IEEE
87views VLSI» more  VLSID 1999»
9 years 9 months ago
Optimal Retiming for Initial State Computation
Retiming is a transformation that optimizes a sequential circuit by relocating the registers. When the circuit has an initial state, one must compute an equivalent initial state f...
Peichen Pan, Guohua Chen
VLSID
1999
IEEE
100views VLSI» more  VLSID 1999»
9 years 9 months ago
Satisfiability-Based Detailed FPGA Routing
In this paper we address the problem of detailed FPGA routing using Boolean formulation methods. In the context of FPGA routing where routing resources are fixed, Boolean formulat...
Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar
VLSID
1999
IEEE
93views VLSI» more  VLSID 1999»
9 years 9 months ago
Spec-Based Repeater Insertion and Wire Sizing for On-chip Interconnect
Recently Lillis, et al. presented an elegant dynamic programming approach to RC interconnect delay optimization through driver sizing, repeater insertion, and, wire sizing which e...
Noel Menezes, Chung-Ping Chen
VLSID
1999
IEEE
97views VLSI» more  VLSID 1999»
9 years 9 months ago
Improving Area Efficiency of Residue Number System based Implementation of DSP Algorithms
Residue Number System based applications involve modulo-arithmetic which is typically implemented using look-up-tables (LUTs) for a small value of modulus. In this paper, we prese...
M. N. Mahesh, Satrajit Gupta, Mahesh Mehendale
VLSID
1999
IEEE
111views VLSI» more  VLSID 1999»
9 years 9 months ago
A New Approach for CMOS Op-Amp Synthesis
A new approach for CMOS op-amp circuit synthesis has proposed here. The approach is based on the observation that the rst order behavior of a MOS transistor in the saturation regi...
Pradip Mandal, V. Visvanathan
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