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2008
ACM

Beyond the arithmetic constraint: depth-optimal mapping of logic chains in LUT-based FPGAs

8 years 10 months ago
Beyond the arithmetic constraint: depth-optimal mapping of logic chains in LUT-based FPGAs
Look-up table based FPGAs have migrated from a niche technology for design prototyping to a valuable end-product component and, in some cases, a replacement for general purpose processors and ASICs alike. One way architects have bridged the performance gap between FPGAs and ASICs is through the inclusion of specialized components such as multipliers, RAM modules, and microcontrollers. Another dedicated structure that has become standard in reconfigurable fabrics is the arithmetic carry chain. Currently, it is only used to map arithmetic operations as identified by HDL macros. For non-arithmetic operations, it is an idle but potentially powerful resource. This work presents ChainMap, a polynomial-time delayoptimal technology mapping algorithm for the creation of generic logic chains in LUT-based FPGAs. ChainMap requires no HDL macros be preserved through the design flow. It creates logic chains, both arithmetic and non-arithmetic, in an arbitrary Boolean network whenever depth increasi...
Michael T. Frederick, Arun K. Somani
Added 26 Oct 2010
Updated 26 Oct 2010
Type Conference
Year 2008
Where FPGA
Authors Michael T. Frederick, Arun K. Somani
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