Binding, Allocation and Floorplanning in Low Power High-Level Synthesis

This work is a contribution to high level synthesis for low power systems. While device feature size decreases, interconnect power becomes a dominating factor. Thus it is important that accurate physical information is used during high-level synthesis [1]. We propose a new power optimisation algorithm for RTlevel netlists. The optimisation performs simultaneously slicingtree structure-based floorplanning and functional unit binding and allocation. Since floorplanning, binding and allocation can use the information generated by the other step, the algorithm can greatly optimise the interconnect power. Compared to interconnect unaware power optimised circuits, it shows that interconnect power

• Type: Conference
• Year: 2003
• Where: ICCAD
• Authors: Ansgar Stammermann, Domenik Helms, Milan Schulte, Arne Schulz, Wolfgang Nebel
• Keywords: Hardware, ICCAD 2003, Interconnect Power, Power Optimisation Algorithm, Power Optimised Circuits