Challenges in exploitation of loop parallelism in embedded applications

Embedded processors have been increasingly exploiting hardware parallelism. Vector units, multiple processors or cores, hyper-threading, special-purpose accelerators such as DSPs or cryptographic engines, or a combination of the above have appeared in a number of processors. They serve to address the increasing performance requirements of modern embedded applications. How this hardware parallelism can be exploited by applications is directly related to the amount of parallelism inherent in a target application. In this paper we evaluate the performance potential of different types of parallelism, viz., true thread-level parallelism, speculative threadlevel parallelism and vector parallelism, when executing loops.

• Type: Conference
• Year: 2006
• Where: CODES
• Authors: Arun Kejariwal, Alexander V. Veidenbaum, Alexandru Nicolau, Milind Girkar, Xinmin Tian, Hideki Saito
• Keywords: CODES 2006, Hardware Parallelism, Hardware-Software Codesign, Speculative Threadlevel Parallelism, True Thread-level Parallelism