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2007

Energy-Aware System Synthesis for Reconfigurable Chip Multiprocessors

10 years 1 months ago
Energy-Aware System Synthesis for Reconfigurable Chip Multiprocessors
- Even though state-of-the-art FPGAs present new opportunities in exploring low-cost high-performance architectures for floating-point scientific applications, they also pose serious challenges. Multiprocessors-on-a-ProgrammableChip (MPoPCs), which integrate both softwareprogrammability and hardware-reconfigurability, provide substantial flexibility that can result in programming ease and high performance. This paper presents an application-oriented system design methodology for HERA (HEterogeneous Reconfigurable Architecture), an in-house developed MPoPC that targets applications involving large matrices. HERA is a mixed computing-mode multiprocessor supporting simultaneous execution in SIMD (Single-Instruction, Multiple-Data), MIMD (Multiple-Instruction, Multiple-Data), and multiple-SIMD for chosen groups of processors. Given an application with specific energy-performance objectives, our design methodology aims to customize HERA to match the diverse computation and communication cha...
Xiaofang Wang, Sotirios G. Ziavras, Jie Hu
Added 29 Oct 2010
Updated 29 Oct 2010
Type Conference
Year 2007
Where ERSA
Authors Xiaofang Wang, Sotirios G. Ziavras, Jie Hu
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