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CCS
2007
ACM

Compact FPGA implementations of QUAD

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Compact FPGA implementations of QUAD
QUAD is a stream cipher whose provable security relies on the hardness of solving systems of multivariate quadratic equations. This paper explores FPGA implementations of the stream cipher QUAD and, more specifically, small area ones. Our smallest implementation of QUAD requires only 85 slices (2961 GE) on a Virtex 4 Xilinx FPGA, which makes it not only the smallest provably secure stream cipher, but also a very good competitor among conventional stream ciphers. In particular, we demonstrate an implementation of QUAD’s underlying PRNG which results in a 68% improvement over the smallest known AES implementation on FPGA [13]. Categories and Subject Descriptors B.m [Hardware]: Miscellaneous; E.3 [Data]: Data Encryption Keywords FPGA, RFID, stream cipher, PRNG, forward security, user privacy, hardware implementation.
David Arditti, Côme Berbain, Olivier Billet,
Added 07 Jun 2010
Updated 07 Jun 2010
Type Conference
Year 2007
Where CCS
Authors David Arditti, Côme Berbain, Olivier Billet, Henri Gilbert
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