Very Compact FPGA Implementation of the AES Algorithm

11 years 6 months ago
Very Compact FPGA Implementation of the AES Algorithm
Abstract. In this paper a compact FPGA architecture for the AES algorithm with 128-bit key targeted for low-cost embedded applications is presented. Encryption, decryption and key schedule are all implemented using small resources of only 222 Slices and 3 Block RAMs. This implementation easily fits in a low-cost Xilinx Spartan II XC2S30 FPGA. This implementation can encrypt and decrypt data streams of 150 Mbps, which satisfies the needs of most embedded applications, including wireless communication. Specific features of Spartan II FPGAs enabling compact logic implementation are explored, and a new way of implementing MixColumns and InvMixColumns transformations using shared logic resources is presented.
Pawel Chodowiec, Kris Gaj
Added 06 Jul 2010
Updated 06 Jul 2010
Type Conference
Year 2003
Where CHES
Authors Pawel Chodowiec, Kris Gaj
Comments (0)