A Compiler-in-the-Loop framework to explore Horizontally Partitioned Cache architectures

Horizontally Partitioned Caches (HPCs) are a promising architectural feature to reduce the energy consumption of the memory subsystem. However, the energy reduction obtained using HPC architectures is very sensitive to the HPC parameters. Therefore it is very important to explore the HPC design space and carefuly choose the HPC parameters that result in minimum energy consumption for the application. However, since in HPC architectures, the compiler has a significant impact on the energy consumption of the memory subsystem, it is extremely important to include compiler while deciding the HPC design parameters. While there has been no previous apporaches to HPC design exploration, existing cache design space exploration methodologies do not include the compiler effectsduring DSE. In this paper, we present a Compilerin-the-Loop (CIL) Design Space Exploration (DSE) methodology to explore and decide the HPC design parameters. Our experimental results on HP iPAQ h4300-like memory subsystem...

• Type: Conference
• Year: 2008
• Where: ASPDAC
• Authors: Aviral Shrivastava, Ilya Issenin, Nikil Dutt
• Keywords: ASPDAC 2008, Energy Consumption, Hardware, HPC Design, HPC Design Parameters