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2008
IEEE

Configurable and scalable high throughput turbo decoder architecture for multiple 4G wireless standards

9 years 4 days ago
Configurable and scalable high throughput turbo decoder architecture for multiple 4G wireless standards
In this paper, we propose a novel multi-code turbo decoder architecture for 4G wireless systems. To support various 4G standards, a configurable multi-mode MAP (maximum a posteriori) decoder is designed for both binary and duo-binary turbo codes with small resource overhead (less than 10%) compared to the single-mode architecture. To achieve high data rates in 4G, we present a parallel turbo decoder architecture with scalable parallelism tailored to the given throughput requirements. High-level parallelism is achieved by employing contention-free interleavers. Multi-banked memory structure and routing network among memories and MAP decoders are designed to operate at full speed with parallel interleavers. We designed a very low-complexity recursive on-line address generator supporting multiple interleaving patterns, which avoids the interleaver address memory. Design trade-offs in terms of area and power efficiency are explored to find the optimal architectures. A 711 Mbps data rate i...
Yang Sun, Yuming Zhu, Manish Goel, Joseph R. Caval
Added 12 Oct 2010
Updated 12 Oct 2010
Type Conference
Year 2008
Where ASAP
Authors Yang Sun, Yuming Zhu, Manish Goel, Joseph R. Cavallaro
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