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ASAP
2008
IEEE
105views Hardware» more  ASAP 2008»
8 years 5 months ago
Fast custom instruction identification by convex subgraph enumeration
Automatic generation of custom instruction processors from high-level application descriptions enables fast design space exploration, while offering very favorable performance and...
Kubilay Atasu, Oskar Mencer, Wayne Luk, Can C. &Ou...
ASAP
2008
IEEE
199views Hardware» more  ASAP 2008»
8 years 5 months ago
An efficient method for evaluating polynomial and rational function approximations
In this paper we extend the domain of applicability of the E-method [7, 8], as a hardware-oriented method for evaluating elementary functions using polynomial and rational functio...
Nicolas Brisebarre, Sylvain Chevillard, Milos D. E...
ASAP
2008
IEEE
119views Hardware» more  ASAP 2008»
8 years 5 months ago
An FPGA architecture for CABAC decoding in manycore systems
Arithmetic coding is an efficient entropy compression method that achieves results close to the entropy limit and it is used in modern standards such as JPEG-2000 and H.264. Arith...
Roberto R. Osorio, Javier D. Bruguera
ASAP
2008
IEEE
120views Hardware» more  ASAP 2008»
8 years 5 months ago
Lightweight DMA management mechanisms for multiprocessors on FPGA
This paper presents a multiprocessor system on FPGA that adopts Direct Memory Access (DMA) mechanisms to move data between the external memory and the local memory of each process...
Antonino Tumeo, Matteo Monchiero, Gianluca Palermo...
ASAP
2008
IEEE
161views Hardware» more  ASAP 2008»
8 years 5 months ago
Configurable and scalable high throughput turbo decoder architecture for multiple 4G wireless standards
In this paper, we propose a novel multi-code turbo decoder architecture for 4G wireless systems. To support various 4G standards, a configurable multi-mode MAP (maximum a posterio...
Yang Sun, Yuming Zhu, Manish Goel, Joseph R. Caval...
ASAP
2008
IEEE
117views Hardware» more  ASAP 2008»
8 years 5 months ago
Reconfigurable acceleration of microphone array algorithms for speech enhancement
Microphone arrays play an important role in noise reduction and speech enhancement. Their algorithms are based on beamforming, which reduces the level of localized and ambient noi...
Ka Fai Cedric Yiu, Chun Hok Ho, Nedelko Grbic, Yao...
ASAP
2008
IEEE
135views Hardware» more  ASAP 2008»
8 years 9 months ago
On the high-throughput implementation of RIPEMD-160 hash algorithm
Miroslav Knezevic, Kazuo Sakiyama, Yong Ki Lee, In...
ASAP
2008
IEEE
182views Hardware» more  ASAP 2008»
8 years 9 months ago
Low-cost implementations of NTRU for pervasive security
NTRU is a public-key cryptosystem based on the shortest vector problem in a lattice which is an alternative to RSA and ECC. This work presents a compact and low power NTRU design ...
Ali Can Atici, Lejla Batina, Junfeng Fan, Ingrid V...
ASAP
2008
IEEE
145views Hardware» more  ASAP 2008»
8 years 9 months ago
An MPSoC architecture for the Multiple Target Tracking application in driver assistant system
This article discusses the design of an application specific MPSoC architecture dedicated to Multiple Target Tracking (MTT). This application has its utility in driver assistant s...
Jehangir Khan, Smaïl Niar, Atika Rivenq, Yass...
ASAP
2008
IEEE
142views Hardware» more  ASAP 2008»
8 years 9 months ago
Managing multi-core soft-error reliability through utility-driven cross domain optimization
As semiconductor processing technology continues to scale down, managing reliability becomes an increasingly difficult challenge in high-performance microprocessor design. Transie...
Wangyuan Zhang, Tao Li
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