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FPL
2005
Springer

A Configuration Memory Architecture for Fast Run-Time-Reconfiguration of FPGAs

11 years 7 months ago
A Configuration Memory Architecture for Fast Run-Time-Reconfiguration of FPGAs
This paper presents a configuration memory architecture that offers fast FPGA reconfiguration. The underlying principle behind the design is the use of fine-grained partial reconfiguration that allows significant configuration re-use while switching from one circuit to another. The proposed configuration memory works by reading on-chip configuration data into a buffer, modifying them based on the externally supplied data and writing them back to their original registers. A prototype implementation of the proposed design in a 90nm cell library indicates that the new memory adds less than 1% area to a commercially available FPGA implemented using the same library. The proposed design reduces the reconfiguration time for a wide set of benchmark circuits by 63%. However, power consumption during reconfiguration increases by a factor of 2.5 because the read-modify-write strategy results in more switching in the memory array.
Usama Malik, Oliver Diessel
Added 27 Jun 2010
Updated 27 Jun 2010
Type Conference
Year 2005
Where FPL
Authors Usama Malik, Oliver Diessel
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