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ASPDAC
2009
ACM

Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors

10 years 9 months ago
Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors
— In three-dimensional (3D) chips, the amount of supply current per package pin is significantly more than in two-dimensional (2D) designs. Therefore, the power supply noise problem, already a major issue in 2D, is even more severe in 3D. CMOS decoupling capacitors (decaps) have been used effectively for controlling power grid noise in the past, but with technology scaling, they have grown increasingly leaky. As an alternative, metal-insulator-metal (MIM) decaps, with high capacitance densities and low leakage current densities, have been proposed. In this paper, we explore the tradeoffs between using MIM decaps and traditional CMOS decaps, and propose a congestion-aware 3D power supply network optimization algorithm to optimize this tradeoff. The algorithm applies a sequence-of-linear-programs based method to find the optimum tradeoff between MIM and CMOS decaps. Experimental results show that power grid noise can be more
Pingqiang Zhou, Karthikk Sridharan, Sachin S. Sapa
Added 22 Jul 2010
Updated 22 Jul 2010
Type Conference
Year 2009
Where ASPDAC
Authors Pingqiang Zhou, Karthikk Sridharan, Sachin S. Sapatnekar
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