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GLVLSI
1999
IEEE

A Correlation Matrix Method of Clock Partitioning for Sequential Circuit Testability

10 years 1 months ago
A Correlation Matrix Method of Clock Partitioning for Sequential Circuit Testability
Yong Chang Kim, Kewal K. Saluja, Vishwani D. Agraw
Added 03 Aug 2010
Updated 03 Aug 2010
Type Conference
Year 1999
Where GLVLSI
Authors Yong Chang Kim, Kewal K. Saluja, Vishwani D. Agrawal
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