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2009
IEEE

Cycle count accurate memory modeling in system level design

9 years 3 months ago
Cycle count accurate memory modeling in system level design
In this paper, we propose an effective automatic generation approach for a Cycle-Count Accurate Memory Model (CCAMM) from the Clocked Finite State Machine (CFSM) of the Cycle Accurate Memory Model (CAMM). Since memory accesses are gradually dominating system activities, a correct and efficient memory timing model is essential to system-level simulation. In general, a CCAMM provides sufficient timing accuracy with low simulation overhead, and hence is preferred over the Simple Fixed Delay Model (SFDM), which has low accuracy, or the CAMM, which has low performance. Our proposed approach can systematically generate the CCAMM and guarantee correctness. The experimental results show that the generated model is as accurate as the Register Transfer Level (RTL) model while running 100X faster. Categories and Subject Descriptors B.3.3 [Memory Structures]: Performance Analysis and Design Aids
Yi-Len Lo, Mao Lin Li, Ren-Song Tsay
Added 14 Aug 2010
Updated 14 Aug 2010
Type Conference
Year 2009
Where CODES
Authors Yi-Len Lo, Mao Lin Li, Ren-Song Tsay
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