6 search results - page 1 / 2 » Deep Submicron CMOS Integrated Circuit Reliability Simulatio... |
ISQED
2005
IEEE
13 years 10 months ago
2005
IEEE
The purpose of the paper is to introduce a new failure rate-based methodology for reliability simulation of deep submicron CMOS integrated circuits. Firstly, two of the state-of-t...
ISCAS
1999
IEEE
13 years 9 months ago
1999
IEEE
-- Noise in deep submicron technology combined with the move towards dynamic circuit techniques for higher performance have raised concerns about reliability and energyefficiency o...
GLVLSI
2003
IEEE
13 years 10 months ago
2003
IEEE
With scaling down to deep submicron and nanometer technologies, noise immunity is becoming a metric of the same importance as power, speed, and area. Smaller feature sizes, low vo...
DAC
2009
ACM
14 years 5 months ago
2009
ACM
Embedded cryptosystems show increased vulnerabilities to implementation attacks such as power analysis. CMOS technology trends are causing increased process variations which impac...
DAC
2004
ACM
14 years 5 months ago
2004
ACM
We present novel and efficient methods for on-line testing in FPGAs. The testing approach uses a ROving TEster (ROTE), which has provable diagnosabilities and is also faster than ...