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2008
IEEE

Design and defect tolerance beyond CMOS

9 years 3 months ago
Design and defect tolerance beyond CMOS
It is well recognized that novel computational models, devices and technologies are needed in order to sustain the remarkable advancement of CMOS-based VLSI circuits and systems. Regardless of the models, devices and technologies, any enhancement/replacement to CMOS must show significant gains in at least one of the key metrics (including speed, power and cost) for at least a subset of application domains currently employing CMOS circuits. In addition, effective defect tolerant techniques are a critical factor for the successful adoption of any new computing device due to the fact that nano-scale structures will have defect rates much higher than today's CMOS chips. The task of identifying application domains that could benefit the most from a new model/device/technology and ensuring that the resultant system meets functional requirements in the presence of defects requires synergistic efforts of physical scientists, and circuit and system design researchers. This paper contains ...
Xiaobo Sharon Hu, Alexander Khitun, Konstantin K.
Added 18 Oct 2010
Updated 18 Oct 2010
Type Conference
Year 2008
Where CODES
Authors Xiaobo Sharon Hu, Alexander Khitun, Konstantin K. Likharev, Michael T. Niemier, Mingqiang Bao, Kang L. Wang
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