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CSREAESA
2006

Design and Implementation of SoPC with Multi-Bus on a Chip

9 years 8 months ago
Design and Implementation of SoPC with Multi-Bus on a Chip
SoPC (System on a Programmable Chip) is one important kind of SoC solution based on PLD (Programmable Logic Device). At the same time, PBD (Platform-based Design) has become popular and hot on the SoPC design. However, single-bus architecture has been widely adopted in the design of SoPC using PBD. Therefore, many applications, especially those for real-time data processing, suffer from the bottleneck of bus. In our paper, a novel multi-bus SoPC (MBSoPC) architecture design is provided, which adopts multiple PLBs (Processor Local Bus) in one chip. Moreover, a platform based on MBSoPC is built to verify this architecture, which uses three FPGA chips and one of them using three PLBs to act as the main controller. The other two are connected as coprocessor to speed up some critical processing, such as FFT or DCT used commonly in imaging and video processing. We use the MBSoPC platform for real-time image processing. The results show that this architecture can improve system performance s...
Fangjun Jian, Jizhong Han, Chengde Han, Qin Zhang,
Added 30 Oct 2010
Updated 30 Oct 2010
Type Conference
Year 2006
Where CSREAESA
Authors Fangjun Jian, Jizhong Han, Chengde Han, Qin Zhang, Xuhui Liu
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