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DATE
2009
IEEE

Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis

9 years 6 months ago
Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis
– The quest for technologies with superior device characteristics has showcased Carbon Nanotube Field Effect Transistors (CNFETs) into limelight. Among the several design aspects necessary for today's grail in CNFET technology, achieving functional immunity to Carbon Nanotube (CNT) manufacturing issues (such as mispositioned CNTs and metallic CNTs) is of paramount importance. In this work we present a new design technique to build compact layouts while ensuring 100% functional immunity to mispositioned CNTs. Then, as second contribution of this work, we have developed a CNFET Design Kit (DK) to realize a complete design flow from logic-toGDSII traversing the conventional CMOS design flow. This flow enables a framework that allows accurate comparison between CMOS and CNFET-based circuits. This paper also presents simulation results to illustrate such analysis, namely, a CNFETbased inverter can achieve gains, with respect to the EnergyDelay Product (EDP) metric, of more than 4x in...
Shashikanth Bobba, Jie Zhang, Antonio Pullini, Dav
Added 20 May 2010
Updated 20 May 2010
Type Conference
Year 2009
Where DATE
Authors Shashikanth Bobba, Jie Zhang, Antonio Pullini, David Atienza, Giovanni De Micheli
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